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DATA SHEET
MOS INTEGRATED CIRCUIT
PD75206
4-BIT SINGLE-CHIP MICROCOMPUTER
DESCRIPTION
The PD75206 is a microcomputer with a CPU capable of 1-, 4-, and 8-bit-wise data processing, a ROM, a RAM, I/O ports, a fluorescent display tube controller/driver, a watch timer, a timer/pulse generator capable of outputting 14-bit PWM, a serial interface and a vectored interrupt function integrated on a single-chip. It uses the VCR, ECR and CD fluorescent display tubes as display devices and is most suitable for applications requiring the timer/watch function and high-speed interrupt servicing. It can help to provide the unit with many functions and to decrease performance costs. With the PD75206, the PD75P216A, 75P218 one-time PROM products are available for system development evaluation or small production. Detailed functions, etc. are described in the following user's manual. Be sure to read the manual for designing. PD75216A User's Manual: IEM-988
5
FEATURES
* Architecture equal to that of an 8-bit microcomputer * High-speed operation : Minimum instruction execution time : 0.95 s (when operated at 4.19 MHz) * * * * Instruction execution time variable function realizing a wide range of operating voltages On-chip large-capacity program memory : 6K bytes Watch operation with an ultra low current consumption : 5A TYP. (at the 3 V operation) On-chip programmable fluorescent display tube controller/driver
* Timer function : 4 ch * 14-bit PWM output capability with the voltage synthesizer type electronic tuner * Buzzer output capability * Interrupt function with importance attached to applications * For power-off detection * For remote controlled reception * Product with an on-chip PROM : PD75P216A, PD75P218 (on-chip EPROM : WQFN package)
5 5
ORDERING INFORMATION
Ordering Code Package 64-pin plastic shrink DIP (750 mil) 64-pin plastic QFP (14 x 20 mm) Quality Grade Standard Standard
PD75206CW-xxx PD75206GF-xxx-3BE
Please refer to "Quality grade on NEC Semiconductor Devices" (Document number IEI-1209) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
The information in this document is subject to change without notice. Document No. IC-1876A (O. D. No. IC-6969C) Date Published August 1993 P Printed in Japan
The mark 5 shows major revised points. (c) NEC Corporation 1991
PD75206
5
LIST OF FUNCTIONS
Item Instruction execution time
Function * 0.95, 1.91, 15.3 s (Main system clock : 4.19 MHz operation) * 122 s (Subsystem clock : 32.768 kHz operation) 6016 x 8 bits 369 x 4 bits * 4-bit manipulation : 8 x 4 banks * 8-bit manipulation : 4 x 4 banks 33 8 20 CMOS input pin CMOS input/output pins * Direct LED drive capability : 8 * On-chip pull-down resistor by mask option capability : 4 * Direct LED drive capability : 4 * PWM/pulse output : 1 * On-chip pull-down resistor by mask option capability : 4
On-chip memory
ROM RAM
General register
Input/output port
FIP (R) dual-function pin included FIP dedicated pin excluded
FIP controller/driver
Timer
Serial interface
Vectored interrupt Test input System clock oscillator
Standby function Mask option
Operating temperature range Operating voltage Package
2

* * * * *
5
CMOS output pin
No. of segments : 9 to 12 segments No. of digits : 9 to 16 digits Dimmer function : 8 levels On-chip pull-down resistor by mask option capability Key scan interrupt generation * * * * Timer/pulse generator : 14-bit PWM output enabled Watch timer : Buzzer output enabled Timer/event counter Basic interval timer : Watchdog timer application capability
4 channels
* MSB start/LSB start switchable * Serial bus configuration capability External : 3, Internal : 5 External : 1, Internal : 1 * Ceramic/crystal oscillator for main system clock oscillation : 4.194304 MHz standard * Crystal oscillator for subsystem clock oscillation : 32.768 kHz standard STOP/HALT mode * Power-on reset, power-on flag * High withstand voltage port : Pull-down resistor or open-drain output * Port 6 : Pull-down resistor -40 to +85 C 2.7 to 6.0 V (standby data hold : 2.0 to 6.0 V) * 64-pin plastic shrink DIP (750 mil) * 64-pin plastic QFP (14 x 20 mm)
PD75206
CONTENTS 1. 2. 3. PIN CONFIGURATION (TOP VIEW) ....................................................................................................... 5 BLOCK DIAGRAM ................................................................................................................................... 6 PIN FUNCTIONS ......................................................................................................................................7
3.1 3.2 3.3 3.4 3.5 3.6 PORT PINS ......................................................................................................................................................... 7 NON-PORT PINS ............................................................................................................................................... 8 PIN INPUT/OUTPUT CIRCUIT LIST ................................................................................................................. 9 UNUSED PINS TREATMENT ......................................................................................................................... 10 P00/INT4 PIN AND RESET PIN OPERATING PRECAUTIONS .................................................................... 11 XT1, XT2 AND P50 PIN OPERATING PRECAUTIONS ................................................................................ 11
4. 5.
PD75206 ARCHITECTURE AND MEMORY MAP.............................................................................. 12
PERIPHERAL HARDWARE FUNCTIONS ............................................................................................. 14
5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 PORTS .............................................................................................................................................................. 14 CLOCK GENERATOR CIRCUIT ...................................................................................................................... 15 BASIC INTERVAL TIMER ............................................................................................................................... 16 WATCH TIMER ................................................................................................................................................ 17 TIMER/EVENT COUNTER............................................................................................................................... 18 TIMER/PULSE GENERATOR .......................................................................................................................... 19 SERIAL INTERFACE ........................................................................................................................................ 20 FIP CONTROLLER/DRIVER ............................................................................................................................. 22 POWER-ON FLAG (MASK OPTION) ............................................................................................................. 23
6. 7. 8. 9.
INTERRUPT FUNCTIONS ...................................................................................................................... 23 STANDBY FUNCTIONS ......................................................................................................................... 25 RESET FUNCTIONS ............................................................................................................................... 25 INSTRUCTION SET ................................................................................................................................ 26
10. MASK OPTION SELECTION ..................................................................................................................35
11. APPLICATION BLOCK DIAGRAM ........................................................................................................................... 36 11.1 VCR TIMER TUNER ........................................................................................................................................ 36 11.2 COMPACT DISK PLAYER ............................................................................................................................... 37 11.3 ECR ................................................................................................................................................................... 37 12. ELECTRICAL SPECIFICATIONS .............................................................................................................................. 38
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PD75206
13. CHARACTERISTIC CURVES .................................................................................................................................... 51 14. PACKAGE INFORMATION ...................................................................................................................................... 55 15. RECOMMEDED SOLDERING CONDITIONS ......................................................................................................... 58
APPENDIX A. APPENDIX B.
DEVELOPMENT TOOLS ...................................................................................................................... 59 RELATED DOCUMENTS ..................................................................................................................... 60
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PD75206
1.
PIN CONFIGURATION (TOP VIEW)
S3 S2 S1 S0 P00/INT4 P01/SCK P02/SO P03/SI P10/INT0 P11/INT1 P12/INT2 P13/TI0 P20 P21 P22 P23/BUZ P30 P31 P32 P33 P60 P61 P62 P63 P40 P41 P42 P43 PPO X1 X2 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
VDD S4 S5 S6 S7 S8 S9 VPRE VLOAD T15/S10 T14/S11 T13/PH0 T12/PH1 T11/PH2 T10/PH3 T9 T8 T7 T6 T5 T4 T3 T2 T1 T0 RESET P53 P52 P51 P50 XT2 XT1
P12/INT2
P11/INT1
P10/INT0
P23/BUZ
P13/TI0
P41 P42 P43 PPO X1 X2 VSS XT1 XT2 P50 P51 P52 P53
51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 52 32 53 54 55 56 57 58 59 60 61 62 63 64 1 2 3 4 5 6 7 8 31 30 29 28
P02/SO
P03/SI
PD75206CW-xxx
P40
P63
P62
P61
P60
P33
P32
P31
P30
P22
P21
P20
P01/SCK P00/INT4 S0 S1 S2 S3 VDD S4 S5 S6 S7 S8 S9
PD75206GF-xxx-3BE
27 26 25 24 23 22 21
20 9 10 11 12 13 14 15 16 17 18 19
RESET
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
VLOAD
T14/S11
T10/PH3
T11/PH2
T12/PH1
T13/PH0
T15/S10
VPRE
5
6
PORT0 BASIC INTERVAL TIMER INTBT TI0/P13 TIMER/EVENT COUNTER #0 INTT0 TIMER/PULSE GENERATOR PPO INTTPG SI/P03 SO/P02 SCK/P01 INTSIO 4 INT0/P10 INT1/P11 INT2/P12 INTERRUPT CONTROL INTW WATCH TIMER fX/2 N CLOCK DIVIDER SYSTEM CLOCK GENERATOR SUB MAIN STAND BY CONTROL CPU CLOCK INTKS PORTH BUZ/P23 XT1 XT2 X1 X2 VDD VSS RESET 4 PH0-PH3 VPRE VLOAD FIP CONTROLLER/ DRIVER SERIAL INTERFACE ROM PROGRAM MEMORY 6016 x 8 BITS PORT6 DECODE AND CONTROL RAM DATA MEMORY 369 x 4 BITS 4 P60-P63 PROGRAM COUNTER(13) ALU CY SP(8) PORT2 BANK 4 P20-P23 4 P00-P03 PORT1 4 P10-P13 PORT3 4 P30-P33 PORT4 GENERAL REG. 4 P40-P43 PORT5 4 P50-P53 10 T0-T9 T10/PH3- T13/PH0 T14/S11, T15/S10 S0-S9 2 10 INT4/P00
2. BLOCK DIAGRAM
PD75206
PD75206
3. PIN FUNCTIONS
3.1 PORT PINS
Pin Name P00 P01 P02 P03 P10 P11 P12 P13 P20 P21 P22 P23 P30-P33
I/O Input Input/output Input/output Input Input
DualFunction Pin INT4 SCK SO SI INT0 INT1 INT2 TI0
Function 4-bit input port (PORT0).
8-Bit I/O
Input / Output After Reset Circuit Type *1 Input B F G B
x
Noise removing function available Noise removing function available 4-bit input port (PORT1).
Input
B
Input/ output
--- --- --- BUZ
4-bit input/output port (PORT2).
x
Input
E
Input/ output Input/ output Input/ output Input/ output
---
Programmable 4-bit input/ output port (PORT3). Input/output specifiable in 1-bit units. 4-bit input/output port (PORT4). LED direct drive capability. 4-bit input/output port (PORT5). LED direct drive capability. Programmable 4-bit input/output port (PORT6). Input/output specifiable in 1-bit units. On-chip pull-down resistor available (mask option). Suitable for key input.
Input
E
P40 to P43
---
q
Input
E
P50 to P53
---
Input
E
P60 to P63
---
x
Input
V
PH0 PH1 PH2 PH3
Output
T13 T12 T11 T10
4-bit P-ch open-drain, high-dielectric, high-current output port (PORTH). LED direct drive capability. On-chip pull-down resistor available (mask option).
x
Low level (with an onchip pulldown resistor) or high impedance.
I
*
Schmitt trigger inputs are circled.
7
PD75206
3.2
NON-PORT PINS
DualFunction Pin --- FIP controller/ driver output pins. Pull-down resistor can be incorporated in bit units (mask option). Input / Output Circuit Type * I
Pin Name T0 to T9
I/O Output
Function Digit output high-voltage high-current output. Digit/segment output dual-function high-voltage high-current output. Extra pins can be used as PORTH. Digit/segment output dual-function high-voltage high-current output. Static output also possible. Segment output high voltage output. Static output also possible. Segment high-voltage output.
After Reset Low level (With an onchip pulldown resistor ) or high impedance (without a pull-down resistor)
T10 to T13
PH3 to PH0
T14/S11, T15/S10
---
S9
S0 to S8 PPO Output ---
Timer/pulse generator pulse output.
High impedance
D
TI0 SCK SO SI INT4
Input Input/output Input/output Input Input
P13 P01 P02 P03 P00
External event pulse input for timer/event counter. Serial clock input/output. Serial data input pin or serial data input/output. Serial data input or normal input. Edge-detected vectored interrupt input (rising and falling edge detection). Edge-detected vectored interrupt input with noise eliminate function (detection edge selection possible). Edge-detected testable input (rising edge detection). Fixed frequency output (for buzzer or system clock trimming). Crystal/ceramic connect pin for main system clock oscillation. External clock input to X1 and its inverted clock input to X2. Crystal connect pin for subsystem clock oscillation. External clock input to XT1 and XT2 open. System reset input (low level active). Input Input Input Input
B F G B B
INT0 INT1 INT2 BUZ
Input
P10 P11
B
Input Input/output
P12 P23
B E
X1, X2
Input
---
XT1 XT2 RESET VPRE VLOAD VDD VSS
Input --- Input
---
B I I
--- --- --- ---
FIP controller/driver output buffer power supply. FIP controller/driver pull-down resistor connect pin. Positive power supply. GND potential.
*
Schmitt trigger inputs are circled.
8
PD75206
3.3
PIN INPUT/OUTPUT CIRCUIT LIST
TYPE A TYPE F
VDD
data output disable Type D
IN/OUT
P-ch IN N-ch
Type B
CMOS-Specified Input Buffer TYPE B
Input/Output Circuit Consisting of Type D Push-Pull Output and Type B Schmitt Trigger Input TYPE G VDD P-ch output disable data P-ch IN/OUT N-ch Type B
IN
Schmitt Trigger Input Having Hysteresis Characteristics TYPE D VDD data data P-ch OUT output disable Type D IN/OUT Input/Output Circuit Capable of Switching between Push-Pull Output and N-ch Open-Drain Output (with P-ch OFF). TYPE V
output disable
N-ch Type A Pull-down Resistor (Mask Option)
Push-Pull Output which can be Set to Output High Impedance (with Both P-ch and N-ch Set to OFF) TYPE E TYPE I
data output disable Type D
VDD IN/OUT data P-ch
VDD P-ch
OUT
N-ch Type A
Pull-down Resistor (Mask Option) VLOAD VPRE
Input/Output Circuit Consisting of Type D Push-Pull Output and Type A Input Buffer
9
PD75206
3.4
UNUSED PINS TREATMENT
Pin P00/INT4 P01/SCK P02/SO P03/SI P10/INT0 to P12/INT2 P13/TI0 P20 to P22 P23/BUZ P30 to P33 P40 to P43 P50 to P53 P60 to P63 PPO S0 to S9 T15/S10 to T14/S11 T0 to T9 T10/PH3 to T13/PH0 XT1 XT2 RESET when there is an onchip power-on reset circuit VLOAD when there is no onchip load resistor Leave open Connect to VSS Connect to VSS
Recommended Connection
Connect to VSS or VDD
Input state : Connect to VSS or VDD Ouput state : Leave open
Connect to VSS or VDD Leave open Connect to VDD
Connect to VSS or VDD
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PD75206
3.5 P00/INT4 PIN AND RESET PIN OPERATING PRECAUTIONS P00/INT4 and RESET pins have the function (especially for IC test) to test PD75206 internal operations in addition to the functions described in sections 3.1 and 3.2. The test mode is set when a voltage larger than VDD is applied to one of these pins. If noise larger than VDD is applied in normal operation, the test mode may be set thereby adversely affecting normal operation. Since there is a display output pin having a high-voltage amplitude (35 V) next to the P00/INT4 and RESET pins, if cables for the related signals are routed in parallel, wiring noise larger than VDD may be applied to the P00/INT4 and RESET pins causing errors. Thus, carry out wiring so that wiring noise can be minimized, If noise still cannot be suppressed, take the measure against noise using the following external components. * Connect diode with small VF (0.3 V or less) between VDD and P00/INT4.RESET
VDD
*
Connect a capacitor between the pins and VDD.
VDD
VDD
VDD
P00/INT4, RESET
P00/INT4, RESET
3.6 XT1, XT2 AND P50 PIN OPERATING PRECAUTIONS When selecting the 32.768 kHz subsystem clock connected to the XT1 and XT2 pins as the watch timer source clock, the signal to be input or output to the P50 pin next to the XT2 pin must be a signal required to be switched between high and low the minimum number of times (once/second or less). If the P50 pin signal is switched frequently between high and low, a spike is generated in the XT2 pin because of capacitance coupling of the P50 and XT2 pins and the correct watch functions cannot be achieved (the watch becomes fast). If it is necessary to allow the P50 pin signal to switch between high and low, mount an external capacitor to the P50 pin as shown below.
PD75206
P50 XT1 XT2 0.0068 F 32.768 kHz
11
PD75206
4. PD75206 ARCHITECTURE AND MEMORY MAP
The PD75206 has the following three architectural features. * Data memory bank configuration: Static RAM (320 words x 4 bits) Display data memory (49 words x 4 bits) Peripheral hardware (128 x 4 bits) * General register bank configuration: 8 x 4 banks (Operated in 4 bits) 4 x 4 banks (Operated in 8 bits) * Memory mapped I/O Figures 4-1, 4-2 shows memory maps of PD75206.
Fig. 4-1 Program Memory Map
Address 7 0000H 0002H 0004H 0006H 0008H 000AH 000CH 000EH MBE MBE MBE MBE MBE MBE MBE MBE 6 RBE RBE RBE RBE RBE RBE RBE RBE 5 0 0 0 0 0 0 0 0 0 Internal Reset Start Address (Most Significant 5 Bits) Internal Reset Start Address (Least Significant 8 Bits) INTBT/INT4 Start Address INTBT/INT4 Start Address INT0 Start Address INT0 Start Address INT1 Start Address INT1 Start Address INTSIO Start Address INTSIO Start Address INTT0 Start Address INTT0 Start Address INTTPG Start Address INTTPG Start Address INTKS Start Address INTKS Start Address (Most Significant 5 Bits) (Least Significant 8 Bits) (Most Significant 5 Bits) (Least Significant 8 Bits) (Most Significant 5 Bits) (Least Significant 8 Bits) (Most Significant 5 Bits) (Least Significant 8 Bits) (Most Significant 5 Bits) (Least Significant 8 Bits) (Most Significant 5 Bits) (Least Significant 8 Bits) (Most Significant 5 Bits) (Least Significant 8 Bits) CALLF !faddr Instruction Entry Address
BRCB !caddr Instruction Branch Address CALL !addr Instruction Subroutine Entry Address BR !addr Instruction Branch Address
0020H GETI Instruction Reference Table 007FH 0080H BR $addr Instruction Relative Branch Address (-15 to -1 and +2 to +16)
07FFH 0800H Branch Destination Address and Subroutine Entry Address to be Set by GETI Instruction
0FFFH 1000H
177FH
Remarks
In all cases other than those listed above, branch to the address with only the lower 8 bits of the PC changed is enabled by BR PCDE and BR PCXA instructions.
12
PD75206
Fig. 4-2 Data Memory Map
Data Memory General Register Area Stack Area Static RAM (320x 4) 0FFH 100H 64 x 4 13FH Not Incorporated Static RAM (49 x 4) Display Data Memory, etc. 1C0H 49 x 4 1FFH Not Incorporated F80H Peripheral Hardware Area FFFH 128 x 4 Bank 15 Bank 1 Bank 1 256 x 4 000H (32 x 4) 01FH Bank 0
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PD75206
5. PERIPHERAL HARDWARE FUNCTIONS
5.1 PORTS The following three types of I/O ports are provided: * CMOS input * CMOS I/O
:8 : 20
* P-ch open-drain, high-voltage, high-current output : 4 Total : 32 Table 5-1 Port Function
Port name PORT0 4-bit input PORT1 Function Operation, feature Can always be read or tested regardless of operation mode of multiplexed pin. Can always be read or tested. P10 and P11 are provided with noise rejection function. PORT2 PORT4 PORT5 PORT3 PORT6 PORTH 4-bit output 4-bit I/O Remarks: Multiplexed with SI, SO, SCK, and INT4 pins. Multiplexed witn INT0-2 and TI0 pins.
Can be set in input or output mode in 4-bit units. Ports 4 and 5 P23 is multiplexed witn BUZ can be usd in pairs to input/output 8-bit data. Ports 4 and 5 can directly drive LED. Can be set in input or output mode in 1-bit units. Port 6 can be connected to internal pull-down resistor by the mask option. P-ch open-drain, high-voltage, high-current output port. Can directly drive FIP and LED. Can be connected to internal pulldown resistor in 1-bit units by the mask option. Multiplexed with T10-T13 pins. pin.
14
PD75206
5.2
CLOCK GENERATOR CIRCUIT The operation of the clock generator circuit is determined by the processor clock control register (PPC) and
system clock control register (SCC). This circuit can generate two types of clocks: main system clock and subsystem clock. In addition, it can also change the instruction execution time. * 0.95 s, 1.91 s, 15.3 s (main system clock: 4.19 MHz) * 122 s (subsystem clock: 32.768 kHz) Fig. 5-1 Clock Generator Block Diagram
XT1 Subsystem Clock Generator fXT Watch Timer Timer/Pulse Generator Main System Clock Generator Selector 1/8~1/4096 fXX Frequency Divider 1/2 1/6 SCC SCC3 Selector SCC0 PCC Internal Bus PCC0 Oscillation Stop Frequency Divider 1/4 * FIP Controller * Basic Interval Timer (BT) * Timer/Event Counter * Serial Interface * Watch Timer * INT0 Noise Eliminator
XT2 X1
X2
fX
* CPU * INT0 Noise Eliminator * INT1 Noise Eliminator
PCC1 4 HALT F/F HALT* STOP* PCC2 PCC3 R Q S
PCC2 and PCC3 Clear
STOP F/F Q S
Wait Release Signal from BT
RES Signal (Internal Reset) R
Standby Release Signal from Interrupt Control Circuit
*
Instruction execution 1. 2. 3. 4. 5. 6. 7. fX = Main system clock frequency fXT = Subsystem clock frequency fXX = System clock frequency
Remarks
= CPU clock PCC: Processor clock control register SCC: System clock control register 1 clock cycle (tCY) of is 1 machine cycle of an instruction. For tCY, see "AC Characteristics" in 12. ELECTRICAL SPECIFICATIONS. 15
5
PD75206
5.3
BASIC INTERVAL TIMER
The basic interval timer has the following functions: * * * * Interval timer operation to generate reference time Watchdog timer application to detect inadvertent program loop Wait time select and count upon standby mode release Count contents read Fig. 5-2 Basic Interval Timer Configuration
From Clock Generator fXX/2
5
Clear
Clear
fXX/2
7
MPX fXX/2 fXX/2
9
Basic Interval Timer (8-Bit Frequency Divider)
Set
BT Interrupt Request Flag
12
BT
IRQBT
Vectored Interrupt Request Signal
3 Wait Release Signal during Standby Release
BTM3
BTM2
BTM1
BTM0 BTM
SET1*
4 Internal Bus
8
*
Instruction execution
16
PD75206
5.4
WATCH TIMER
The PD75206 incorporates one channel of watch timer. The watch timer has the following functions. * Sets the test flag (IRQW) at 0.5 sec intervals. The standby mode can be released by IRQW. * 0.5 second interval can be set with the main system clock and subsystem clock. * The fast mode enables to set 128-time (3.91 ms) interval useful to program debugging and inspection. * The fixed frequencies (2.048 kHz) can be output to the P23/BUZ pin for use to generate buzzer sound and trim the system clock oscillator frequency. * Since the frequency divider can be cleared, the watch can be started from zero second. Fig. 5-3 Watch Timer Block Diagram
fW (256 Hz : 3.91 ms) 7 2 fXX 128 (32.768 kHz) fXT (32.768 kHz) Selector INTW IRQW Set Signal
From Clock Generator
Selector
fW
(32.768 kHz)
fW 14 2 Frequency Divider 2Hz 0.5 sec fW 16 (2.048 kHz) Clear
Output Buffer P23/BUZ
WM WM7 WM6 WM5 WM4 WM3WM2 WM1 WM0
PORT2.3 P23 Output Latch
Bit 2 of PMGB Port 2 Input/Output Mode
8
Internal Bus
Remarks
Values at fXX = 4.194304 MHz and fXT = 32.768 kHz are indicated in parentheses.
17
PD75206
5.5
TIMER/EVENT COUNTER
The PD75206 incorporates one channel of timer/event counter. The timer/event counter has the following functions. * Program interval timer operation * Event counter operation * Count state read function Fig. 5-4 Timer/Event Counter Block Diagram
Internal Bus SET1 * 8
TM0
8 8 Modulo Register (8) TMOD0
TMn7 TMn6 TMn5 TMn4 TMn3 TMn2 TMn1 TMn0
8 Comparator (8) Input Buffer 8 T0 P13/TI0 From Clock Generator (Refer to Fig. 5-1) MPX Count Register (8) CP Clear Timer Operation Start
Match INTT0 IRQT0 Set Signal
IRQT0 Clear
*
Instruction execution.
18
PD75206
5.6
TIMER/PULSE GENERATOR
The PD75206 incorporates one channel of timer/pulse generator which can be used as a timer or a pulse generator. The timer/pulse generator has the following functions. (a) Functions available in the timer mode * 8-bit interval timer operation (IRQTPG generation) enabling the clock source to be varied at 5 levels * Square wave output to PPO pin (b) Functions available in the PWM pulse generate mode * 14-bit accuracy PWM pulse output to the PPO pin (Used as a digital-to-analog converter and applicable to tuning) 215 * Fixed time interval ( = 7.81 ms : at 4.19 MHz operation) interrupt generation fXX If pulse output is not necessary, the PPO pin can be used as a 1-bit output port. Note If the STOP mode is set while the timer/pulse generator is in operation, miss-operation may result. To prevent that from occurring, preset the timer/pulse generator to the stop state using its mode register. Fig. 5-5 Block Diagram of Timer/Pulse Generator (Timer Mode)
Internal Bus
8 MODL Modulo Register L (8) TPGM3 (Set to "1")
8 MODH Modulo Register L (8)
Modulo Latch H (8) 8 Match Comparator (8) Frequency Divider fX 1/2 TPGM1 Prescalar Select Latch (5) Clear T F/F Set Selector
INTTPG IRQTPG Set Signal
Output Buffer
PPO CP 8 Count Register (8) Clear
TPGM4TPGM5 TPGM7
19
PD75206
Fig. 5-6 Timer/Pulse Generator Block Diagram (PWM Pulse Generate Mode)
Internal Bus
8 MODH Modulo Register H (8) TPGM3
8 MODL Modulo Register L (6) (2)
MODH (8) Modulo Latch (14)
MODL7-2 (6) Output Buffer
TPGM1 fx 1/2
PWM Pulse Generator
Selector
PPO
Frequency Divider INTTPG TPGM5 (IRQTPG Set Signal) 215 ( = 7.81 ms : at 4.19 MHz operation) fX
TPGM7
5.7
SERIAL INTERFACE
The serial interface has the following functions: * Clocked 8-bit transmission/reception operation (synchronous transmission/reception) * * Clocked 8-bit serial bus operation (inputs/outputs data via SO pin. SO output is of N-ch open-drain.) LSB first/MSB first selectable
These features allows the serial interface to communicate data with the serial bus of the other microcomputers such as PD7500 series and 78K series and to be connected with peripheral devices.
20
Fig 5-7 Serial Interface Block Diagram
Internal Bus 8 P03/SI 8 8 SIO7 SIO Shift Register (8) SIOM7SIOM6SIOM5SIOM4SIOM3SIOM2SIOM1SIOM0 SET1 *2 SIOM
Selector
SIO0
*1 P02/SO
SO Output Latch
Serial Clock Counter (3)
Overflow
INTSIO IRQSIO Set Signal IRQSIO Clear Signal
Clear P01/SCK R Q S
Serial Start
fxx/2 MPX fxx/2
4
10
PD75206
*
1. CMOS output and N-ch open drain output switchable output buffer. 2. Instruction execution
21
PD75206
5.8
FIP CONTROLLER/DRIVER
The FIP controller/driver of the PD75206 has the following functions: * * * * * Automatically read display data memory by means of DMA, and generate segment signals and digit signals. Number of display elements can be freely selected in a range of 9 to 12 segments and 9 to 16 digits, and a total of 26 segments/digits or less. Unused display outputs can be used as static outputs. Luminosity can be adjusted in eight steps by a dimmer function. Can be used for key scan. * Interrupt (IRQKS) occurs when a specified key is scanned. * Key scan data can be output from a segment output pin. High-voltage output pins that can directly drive FIP (40 V). * Sement pins (S0-S9): VOD = 40 V, IOD = 3mA * Digit output pins (T0-T15): VOD = 40 V, IOD = 15 mA Can be connected to pull-down resistor in bit units by mask option. Fig. 5-8 FIP Controller/Driver Block Diagram
*
*
Internal Bus 4 Display Mode Register 4 Digit Select Register 4 Dimmer Select Register Key Scan Flag (KSF)
Display Data Memory (48 x 4 Bits)
Key Scan Registers (KS0, KS1) 12 Segment Data Latch (12)
Port H
Digit Signal Generator
IRQKS Generator Signal
10
2
2
4 Selector
4
10
2
4
High-Voltage Output Buffer 10 S0-S9 2 4 10 T0-T9 VLOAD VPRE
T15/S10, T13/PH0T14/S11 T10/PH3
Note
The FIP controller/driver can only operate in the high and medium speeds (PCC = 0011B or 0010B) of the main system clock (SCC.0 = 0). It may cause errors with any other clock or in the standby mode. Thus, be sure to stop FIP controller operation (DSPM.3 = 0) and then shift the unit to any other clock mode or the standby mode.
22
PD75206
5.9
POWER-ON FLAG (MASK OPTION)
The power-on flag (PONF) is automatically set (1) when the power-on reset circuit is activated and the poweron reset signal is generated. (See Fig. 8-1 Reset Signal Generator) The PONF is mapped at bit 0 of address FD1H in the data memory space and can be tested by the memory bit manipulation instructions (SKT, SKF, SKTCLR) or cleared (CLR1). Note The PONF cannot be set by SET1 instruction.
6. INTERRUPT FUNCTIONS
The PD75206 has eight types of interrupt sources and can generate multiple interrupts with priority order. It is also equipped with two types of test sources. INT2 is an edge detected testable input. The PD75206 interrupt control circuit has the following functions: * * * * * Hardware-controller vectored interrupt function which can control interrupt acknowledge with the interrupt enable flag (IExxx) and the interrupt master enable flag (IME). Function of setting any interrupt start address. Multiple interrupt function which can specify priority order with the interrupt priority select register (IPS). Interrupt request flag (IRQxxx) test function. (Interrupt generation can be checked by software.) Standby mode release function. (Interrupt to be released by interrupt enable flag can be selected.)
23
24 Fig. 6-1 Interrupt Control Circuit Block Diagram
Internal Bus 2 IM1 2 IM0 (IME) Interrupt Enable Flag (IEXXX) Decoder IRQBT IRQ4 IRQ0 IRQ1 IRQSIO IRQT0 IRQTPG IRQKS IRQW IRQ2 Standby Release Signal Priority Control Circuit Vector Table Address Generator Circuit VRQn 4 IPS 2 IST INT BT INT4 /P00 INT0 /P10 INT1 /P11 * *
Both Edges Detection Circuit Edge Detection Circuit Edge Detection Circuit
INTSIO INTT0 INTTPG INTKS INTW INT2 /P12
Rising Edge Detection Circuit
PD75206
PD75206
7. STANDBY FUNCTIONS
Two standby modes (STOP mode and HALT mode) are available for the PD75206 to decrease power consumption in the program standby mode. Table 7-1 Operation Status in Standby Mode
STOP Mode Set instruction System clock when set STOP instruction Setting enabled only with main system clock. Oscillator stops only with main system clock. Operation stopped. HALT Mode HALT instruction Setting enabled with either main system clock or subsystem clock. Stops only with CPU clock (Oscillation continued). Operation (IRQBT set at reference time intervals). Operation enabled when serial clock other than is specified. Operation enabled.
Clock oscillator
Basic interval timer
Operating State
Serial interface
Operation enabled only when external SCK input is selected for serial clock. Operation enabled only when TI0 pin input is specified for count clock. Operation stopped.
Timer/event counter
Timer/pulse generator Watch timer
Operation enabled.
Operation enabled only fXT is selected for Operation enabled. count clock. Operation disabled (display off mode set before disabling). Operation stopped. Interrupt request signal (except INT0, INT1, INT2) or RESET input enabled by interrupt enable flag.
FIP controller/driver CPU Release signal
8. RESET FUNCTIONS
The reset signal (RES) generator has a configuration shown in Fig.8-1. Fig. 8-1 Reset Signal Generator
RESET
Internal Reset Signal (RES) Mask Option Power-On Reset Generator SWB Bit Manipulation Instruction Execution
SWA Power-On Flag (PONF)
The power-on reset generator is a circuit to generate a one-shot pulse upon detection of the start-up of the power voltage. This pulse is used in the three ways according to SWA, SWB mask option specification shown in Fig. 81. (Refer to 10. MASK OPTION SELECTION.) 25
Internal Bus
PD75206
9. INSTRUCTION SET
(1) Operand identifier and description Enter an operand in the operand column of each instruction using the description method relating to the
operand identifier of the instruction (refer to RA75X Assembler Package User's Manual - Language (EEU-730)). If more than one description method is available, select one. Capital alphabetic letters, plus and minus signs are keywords. Describe them as they are. In the case of immediate data, describe appropriate numerical values or labels. * For 8-bit data processing, only even addresses can be specified.
Identifier reg reg 1 rp rp1 rp2 rp' rp'1 rpa rpa1 n4 n8 mem bit fmem pmem addr caddr faddr taddr PORTn IEXXX RBn MBn X, A, B, C, D, E, H, L X, B, C, D, E, H, L
Description Method
XA, BC, DE, HL BC, DE, HL BC, DE XA, BC, DE, HL, XA', BC', DE', HL' BC, DE, HL, XA', BC', DE', HL' HL, HL+, HL-, DE, DL DE, DL 4-bit immediate data or label 8-bit immediate data or label 8-bit immediate data or label* 2-bit immediate data or label FB0H to FBFH and FF0H to FFFH immediate data or labels FC0H to FFFH immediate data or labels 0000H to 177FH immediate data or labels 12-bit immediate data or label 11-bit immediate data or label 20H to 7FH immediate data (bit0 = 0) or label PORT0 to PORT6 IEBT, IESIO, IET0, IETPG, IE0, IE1, IEKS, IEW, IE4 RB0 to RB3 MB0, MB1, MB15
26
PD75206
(2)
Legend for operation description A : A register; 4-bit accumulator B : B register C D E H L X XA BC DE HL XA' BC' DE' HL' PC SP CY PSW MBE RBE PORTn IME IPS IExxx RBS MBS PCC * (xx) xxH : : : : : : : : : : : : : : : : : : : : : : : : : : : : C register D register E register H register L register X register Register pair (XA); 8-bit accumulator Register pair (BC) Register pair (DE) Register pair (HL) Expanded register pair (XA') Expanded register pair (BC') Expanded register pair (DE') Expanded register pair (HL') Program counter Stack pointer Carry flag; Bit accumulator Program status word Memory bank enable flag Register bank enable flag Port n (n Interrupt Interrupt Interrupt = 0 to 6) master enable flag priority select register enable flag
Register bank select register Memory bank select register Processor clock control register Address and bit delimiter
: Contents addressed by xx : Hexadecimal data
27
PD75206
(3)
Description of symbols in the addressing area column
*1
MB = MBE * MBS (MBS = 0, 1, 15) MB = 0 MBE = 0 : MB = 0 (00H to 7FH) MB = 15 (80H to FFH) MBE = 1 : MB = MBS (MBS = 0, 1, 15) MB = 15, fmem = FB0H to FBFH, FF0H to FFFH MB = 15, pmem = FC0H to FFFH addr = 0000H to 177FH addr = (Current PC) - 15 to (Current PC) - 1, (Current PC) + 2 to (Current PC) + 16 caddr = 0000H to 0FFFH 1000H to 177FH faddr = 0000H to 07FFH taddr = 0020H to 007FH (PC12 = 0) or (PC12 = 1) Program Memory Addressing
*2 *3
Data Memory Addressing
*4
*5 *6 *7
*8
*9 *10
Remarks
1. 2. 3. 4.
MB indicates accessible memory bank. In *2, MB = 0 irrespective of MBE and MBS. In *4 and *5, MB = 15 irrespective of MBE and MBS. *6 to *10 indicate addressable areas.
(4)
Description of the machine cycle column S indicates the number of machine cycles required for skip operation by an instruction having skip function. The S value varies as follows: * When not skipped ................................................................................................... S = 0 * When 1-byte or 2-byte instructions are skipped ................................................. S = 1 * When 3-byte instructions are skipped (BR !addr, CALL !addr instruction) ..... S = 2 Note GETI instruction is skipped in one machine cycle. One machine cycle is equal to one cycle(=tCY) of CPU clock and three time periods are available according to PCC setting.
28
PD75206
Note 1 Mnemonic MOV
Operands A, #n4 reg1, #n4 XA, #n8 HL, #n8 rp2, #n8 A, @HL A, @HL+ A, @HL- A, @rpa1 XA, @HL @HL, A @HL, XA A, mem
No. of Machine Bytes Cycle 1 2 2 2 2 1 1 1 1 2 1 2 2 2 2 2 2 2 2 2 1 1 1 1 2 2 2 1 2 1 1 1 2 2 2 2 1 2+S 2+S 1 2 1 2 2 2 2 2 2 2 2 2 1 2+S 2+S 1 2 2 2 1 2 3 3 An4 reg1n4 XAn8 HLn8 rp2n8 A(HL)
Operation
Addressing Area
Skip Condition Stack A
Stack A Stack B
*1 *1 *1 *2 *1 *1 *1 *3 *3 *3 *3 L=0 L = FH
A(HL), then LL+1 A(HL), then LL-1 A(rpa1) XA(HL) (HL)A (HL)XA A(mem) XA(mem) (mem)A (mem)XA Areg XArp' reg1A rp'1XA A(HL) A(HL), then LL+1 A(HL), then LL-1 A(rpa1) XA(HL) A(mem) XA(mem) Areg1 XArp' XA(PC12-8+DE)ROM XA(PC12-8+XA)ROM
Transfer
XA, mem mem, A mem, XA A, reg XA, rp' reg1, A rp'1, XA XCH A, @HL A, @HL+ A, @HL- A, @rpa1 XA, @HL A, mem XA, mem A, reg1 XA, rp' MOVT XA, @PCDE XA, @PCXA
*1 *1 *1 *2 *1 *3 *3 L=0 L = FH
Note 2
Note
1. Instruction Group 2. Table reference
29
PD75206
Note
Mnemonic MOV1
Operand CY, fmem.bit CY, pmem.@L CY, @H+mem.bit fmem.bit, CY pmem.@L, CY @H+mem.bit, CY
No. of Machine Bytes Cycle 2 2 2 2 2 2 1 2 1 2 2 1 2 2 1 2 2 1 2 2 2 1 2 2 2 1 2 2 2 1 2 2 2 2 2 2 2 2 1+S 2+S 1+S 2+S 2+S 1 2 2 1+S 2+S 2+S 1 2 2 2 1 2 2 2 1 2 2 2 1 2 2
Operation CY(fmem.bit) CY(pmem7-2+L3-2.bit(L1-0)) CY(H+mem3-0.bit) (fmem.bit)CY (pmem7-2+L3-2.bit(L1-0))CY (H+mem3-0.bit)CY AA+n4 XAXA+n8 AA+(HL) XAXA+rp' rp'1rp'1+XA A, CYA+(HL)+CY XA, CYXA+rp'+CY rp'1, CYrp'1+XA+CY AA-(HL) XAXA-rp' rp'1rp'1-XA A, CYA-(HL)-CY XA, CYXA-rp'-CY rp'1, CYrp'1-XA-CY AA n4 AA (HL) XAXA rp' rp'1rp'1 XA AA AA n4 (HL) rp' XA
Addressing Area *4 *5 *1 *4 *5 *1
Skip Condition
Bit transfer ADDS
A, #n4 XA, #n8 A, @HL XA, rp' rp'1, XA
carry carry *1 carry carry carry *1
ADDC
A, @HL XA, rp' rp'1, XA
SUBS
A, @HL XA, rp'
*1
borrow borrow borrow
Operation
rp'1, XA SUBC A, @HL XA, rp' rp'1, XA AND A, #n4 A, @HL XA, rp' rp'1, XA OR A, #n4 A, @HL XA, rp' rp'1, XA XOR A, #n4 A, @HL XA, rp' rp'1, XA
*1
*1
*1
XAXA rp'1rp'1 AA AA n4
(HL) rp' XA
*1
XAXA rp'1rp'1
Note
Instruction Group
30
PD75206
Note 1 Mnemonic Note 2 RORC NOT INCS A A reg rp1
Operands
No. of Machine Bytes Cycle 1 2 1 1 2 2 1 2 2 2 1 2 2 2 1 1 1 1 1 2 1+S 1+S 2+S 2+S 1+S 2+S 2+S 2+S 1+S 2+S 2+S 2+S 1 1 1+S 1
Operation CYA0, A3CY, An-1An AA regreg+1 rp1rp1+1 (HL)(HL)+1 (mem)(mem)+1 regreg-1 rp'rp'-1 Skip if reg = n4 Skip if (HL) = n4 Skip if A = (HL) Skip if XA = (HL) Skip if A = reg Skip if XA = rp' CY1 CY0 Skip if CY = 1 CYCY
Addressing Area
Skip Condition
Increment/decrement
reg = 0 rp1 = 00H *1 *3 (HL) = 0 (mem) = 0 reg = FH rp = FFH reg = n4 *1 *1 *1 (HL) = n4 A = (HL) XA = (HL) A = reg XA = rp'
@HL mem DECS reg rp' SKE reg, #n4 @HL, #n4
Compare
A, @HL XA, @HL A, reg XA.rp'
Carry flag manipulation
SET1 CLR1 SKT NOT1
CY CY CY CY
CY = 1
Note
1. Instruction Group 2. Accumulator manipulation
31
PD75206
Note
Mnemonic SET1
Operands mem.bit fmem.bit pmem.@L @H + mem.bit
No. of Machine Bytes Cycle 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 -- 2 2 2 2 2 2 2 2 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2 2 2 2 2 2 2 2 2 --
Operation (mem.bit)1 (fmem.bit)1 (pmem7-2+L3-2.bit(L1-0))1 (H+mem3-0.bit)1 (mem.bit)0 (fmem.bit)0 (pmem7-2+L3-2.bit(L1-0))0 (H+mem3-0.bit)0 Skip if (mem.bit) = 1 Skip if (fmem.bit) = 1 Skip if (pmem7-2+L3-2.bit(L1-0)) = 1 Skip if (H+mem3-0.bit) = 1 Skip if (mem.bit) = 0 Skip if (fmem.bit) = 0 Skip if (pmem7-2+L3-2.bit(L1-0)) = 0 Skip if (H+mem3-0.bit) = 0 Skip if (fmem.bit) = 1 and clear Skip if (pmem7-2+L3-2.bit(L1-0))=1 and clear Skip if (H+mem3-0.bit)=1 and clear CYCY (fmem.bit) CYCY (pmem7-2+L3-2.bit(L1-0)) CYCY (H+mem3-0.bit) CYCY (fmem.bit) CYCY (pmem7-2+L3-2.bit(L1-0)) CYCY (H+mem3-0.bit) CYCY CYCY CYCY (fmem.bit) (pmem7-2+L3-2.bit(L1-0)) (H+mem3-0.bit)
Addressing Area *3 *4 *5 *1 *3 *4 *5 *1 *3 *4 *5 *1 *3 *4 *5 *1 *4 *5 *1 *4 *5 *1 *4 *5 *1 *4 *5 *1 *6
Skip Condition
CLR1
mem.bit fmem.bit pmem.@L @H+mem.bit
SKT
mem.bit fmem.bit pmem.@L
(mem.bit) = 1 (fmem.bit) = 1 (pmem.@L) = 1 (@H+mem.bit) = 1 (mem.bit) = 0 (fmem.bit) = 0 (pmem.@L) = 0 (@H+mem.bit) = 0 (fmem.bit) = 1 (pmem.@L) = 1 (@H+mem.bit)=1
Memory bit manipulation
@H+mem.bit SKF mem.bit fmem.bit pmem.@L @H+mem.bit SKTCLR fmem.bit pmem.@L @H+mem.bit AND1 CY, fmem.bit CY, pmem.@L CY, @H+mem.bit OR1 CY, fmem.bit CY, pmem.@L CY, @H+mem.bit XOR1 CY, fmem.bit CY, pmem.@L CY, @H+mem.bit BR addr
PC12-0addr (Optimum instruction is selected from among BR !addr, BRCB !caddr and BR $addr by an assembler.)
Branch
!addr $addr BRCB BR !caddr PCDE PCXA
3 1 2 2 2
3 2 2 3 3
PC12-0addr PC12-0addr PC12-0PC12+caddr11-0 PC12-0PC12-8+DE PC12-0PC12-8+XA
*6 *7 *8
Note
Instruction Group
32
PD75206
Note
Mnemonic CALL
Operands !addr
No. of Machine Bytes Cycle 3 3
Operation (SP-4) (SP-1) (SP-2)PC11-0 (SP-3) MBE, RBE, 0, PC12 PC12-0addr, SPSP-4 (SP-4) (SP-1) (SP-2)PC11-0 (SP-3) MBE, RBE, 0, PC12 PC12-000, faddr, SPSP-4 MBE, RBE, 0, PC12(SP+1) PC11-0(SP) (SP+3) (SP+2) SPSP+4
Addressing Area *6
Skip Condition
CALLF
!faddr
2
2
*9
RET
1
3
Subroutine stack control
RETS
1
3+S
MBE, RBE, 0, PC12(SP+1) PC11-0(SP) (SP+3) (SP+2) SPSP+4, then skip unconditionally x, x, x, PC12(SP+1) PC11-0(SP) (SP+3) (SP+2) PSW(SP+4) (SP+5), SPSP+6 (SP-1) (SP-2)rp, SPSP-2 (SP-1)MBS, (SP-2)RBS, SPSP-2 rp(SP+1) (SP), SPSP+2 MBS(SP+1), RBS(SP), SPSP+2 IME(IPS.3)1 IExxx1 IME(IPS.3)0 IExxx0 APORTn XAPORTn+1, PORTn PORTnA PORTn+1, PORTnXA Set HALT Mode (PCC.21) Set STOP Mode (PCC.31) No Operation RBSn (n = 0 to 3) (n = 0 to 6) (n = 4) (n = 2 to 6) (n = 4)
Unconditional
RETI
1
3
PUSH
rp BS
1 2 1 2 2
1 2 1 2 2 2 2 2 2 2 2 2 2 2 1 2 2
POP
rp BS
EI Interrupt control IExxx DI IExxx Input/output IN *1 A, PORTn XA, PORTn OUT *1 PORTn, A PORTn, XA HALT STOP NOP SEL RBn MBn
2 2 2 2 2 2 2 2 2 1 2 2
Special CPU control
MBSn (n = 0, 1, 15)
* 1. MBE = 0 or MBE = 1 and MBE = 15 must be set for execution of IN/OUT instruction Note Instruction Group
33
PD75206
Note
Mnemonic GETI *1
Operands taddr
No. of Machine Bytes Cycle 1 3
Operation * TBR instruction PC12-0(taddr)4-0+(taddr+1) ---------------------------------------------------* TCALL instruction (SP-4)(SP-1)(SP-2)PC11-0 (SP-3) MBE, RBE, 0, PC12 PC12-0(taddr)4-0+(taddr+1) SPSP-4 ---------------------------------------------------* (taddr) (taddr+1) instruction executed in the case of instruction except TBR and TCALL instructions
Addressing Area *10
Skip Condition
------------------------
Special
-----------------------Depends on instructions referred to.
* 1. TBR and TCALL instructions are assembled pseudo-instructions to define the GETI instruction table. Note Instruction Group
34
PD75206
10. MASK OPTION SELECTION
The PD75206 has the following mask options enabling or disabling on-chip components. (1) Pin
Pin P60 to P63 T0/T9 T10/PH3 to T13/PH0 T14/S11, T15/S10 S0 to S9 XT1, XT2 Deletion of sybsystem clock oscillator feedback resistor possible Mask Option Pull-up resistor incorporation enabled bit-wise
5
Note
1. In a system not using subsystem clocks, power consumption in the STOP mode can be decreased by removing the feedback resistor from the oscillator. 2. The feedback resistor must be incorporated when use subsystem clock.
(2)
Power-on reset generator, power-on flag (PONF) One of the following three can be selected.
Switch Selection (See Fig. 8-1) SWA ON ON OFF SWB ON OFF OFF
Power-On Reset Generator
Power-On Flag (PONF)
Internal Reset Signal (RES)
Incorporated Incorporated Not incorporated
Incorporated Incorporated Not incorporated
Generate automatically Not generate automatically -----
35
PD75206
11. APPLICATION BLOCK DIAGRAM
11.1 VCR TIMER TUNER
Main Power Supply
+ Super Capacitor
Power Failure Detection
VDD INT4
VSS T0-T15
6
Electronic Tuner
LPF
PPO INT1 SCK SO
PD75206
S0-S11 12
Fluorescent Display Panel (FIP) 12 Segments x 16 Digits
Tape Count Pulse Tape Up/Down SCK System Controller SO Microcomputer SI
Timer Tuner Remote Controlled Reception Tape Counter PORT6 Key Matrix (12 x 4)
PD752104/75106 EEPROMTM PD6252
X1 X2 XT1
INT0
Remote Controlled Signal
PC2800A
BUZ XT2 BZ Piezoelectric Buzzer
36
PD75206
11.2 COMPACT DISK PLAYER
Servo Control IC
SIO
SCK SI/SO
T0-T15 16
S0-S11 12
Fluorescent Display Panel (FIP) 12 Segments x 14 Digits
Loading Circuit
PD75206
Key Matrix (12 x 4)
PORT6 BUZ BZ INT0
Remote Controlled Signal
PC2800A
X1 X2
11.3 ECR
Main Power Supply
+
Power Failure Detection
VDD INT4
VSS T0-T15 16
S0-S9 10 RAM
Fluorescent Display Panel (FIP) 10 Segments x 16 Digits
PD75206
Key Matrix (10 x 4) Printer
PPO BZ X1 X2 XT1 XT2 Piezoelectric Buzzer
37
PD75206
12. ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS (Ta = 25 C)
PARAMETER SYMBOL VDD Power supply voltage VLOAD VPRE Input voltage Output voltage VOD Display output pins 1 pins except display output pins S0 to S9 Output current high IOH T0 to T15 1 pin 1 pin VDD -40 to VDD +0.3 -15 -15 -30 -20 -120 17 60 450 600 -40 to +85 -65 to +150 V mA mA mA mA mA mA mA mW mW C C VI VO Pins except display output pins TEST CONDITIONS RATING -0.3 to +7.0 VDD -40 to VDD +0.3 VDD -12 to VDD +0.3 -0.3 to VDD +0.3 -0.3 to VDD +0.3 UNIT V V V V V
Total of pins except display output pins Total of display output pins Output current low IOL 1 pin Total of pins Total loss*1 Operating temperature Storage temperature PT Topt Tstg Plastic QFP Plastic shrink DIP
POWER SUPPLY VOLTAGE RANGE (Ta = -40 to +85 C)
PARAMETER CPU *2 Display controller Time/pulse generator Other hardware *2
TEST CONDITIONS
MIN. *3 4.5 4.5 2.7
MAX. 6.0 6.0 6.0 6.0
UNIT V V V V
38
PD75206
*
1. Calculation of total loss Design so that the sum of the following three power consumption values for the PD75206CW/GF will be less than the total loss PT (It is recommended to use the system with 80 % or less of the rating). : Given as VDD (MAX.) x IDD1 (MAX.) : There are normal output pin loss and display output pin loss. It is necessary to add a loss derived from the flow of maximum current to each output pin. Pull-down register loss : Power loss due to a pull-down resistor incorporated in the display output pin CPU loss Output pin loss by mask option.
Example
Suppose 4-LED output with 9SEG x 11DIGIT, VDD = 5 V + 10 % and 4.19 MHz oscillation and let a maximum of 3 mA, 15 mA and 10 mA flow to the segment pin, timing pin and LED output pin, respectively. Further, let the voltage of fluorescent display tube (VLOAD voltage) be -30 V and normal voltage be small. CPU loss : 5.5 V x 9.0 mA = 49.5 mW Pin loss : Segment pin ..... 2V x 3 mA x 9 = 54 mW Timing pin ......... 2V x 15 mA = 30 mW 10 x 2 V x 10 mA x 4 = 53 mW 15 (30 + 5.5V)2 x 10 = 504.1 mW Pull-down resistor loss ........ 25 k LED output ........
PT = + + = 690.6 mW In this example, since the allowable total loss is 600 mW for the shrink DIP package, it is necessary to decrease power consumption by decreasing the number of on-chip pull-down resistors. In this example, power consumption can be adjusted to 528.3 mW by incorporating pull-down resistors in only 11 digit outputs and 7 segment outputs and externally mounting pull-down resistors to the 2 remaining segment outputs. 2. Except the system clock oscillator, display controller and timer/pulse generator. 3. The operating voltage range varies depending on the cycle time. Refer to the section describing AC characteristics.
39
PD75206
MAIN SYSTEM CLOCK OSCILLATOR CHARACTERISTICS (Ta = -40 to +85 C, VDD = 2.7 to 6.0 V )
RESONATOR RECOMMENDED CIRCUIT PARAMETER Oscillator frequency (fXX) *2 TEST CONDITIONS VDD = Oscillation voltage range After VDD reaches the minimum value in the oscillation voltage range 2.0 VDD = 4.5 to 6.0 V 4.19 MIN. 2.0 TYP. MAX. 5.0*4 UNIT MHz
X1
Ceramic resonator*1
X2 C2
C1
Oscillation stabilization time *3
4
ms
X1
Crystal resonator
X2 C2
Oscillator frequency (fXX) *2
5.0 *4 10 30
MHz ms ms
C1
Oscillation stabilization time *3
X1
External clock
X2
X1 input frequency (fX) *2
2.0
5.0*4
MHz
PD74HCU04
X1 input high and low level widths (tXH, tXL)
100
250
ns
*
1. Resonators are shown in following page. 2. Oscillator characteristics only. Refer to the description of AC characteristics for details of instruction execution time. 3. Time required for oscillation to become stabilized after VDD application or STOP mode release. 4. When oscillator frequency is " 4.19 < fX 5.0 MHz ", do not select " PCC = 0011 " as instruction execution time. If " PCC = 0011 " is selected, 1 machine cycle becomes less than 0.95 s, with the result that the specified MIN. value of 0.95 s cannot be observed.
5
SUBSYSTEM CLOCK OSCILLATOR CHARACTERISTICS (Ta = -40 to +85 C, VDD = 2.7 to 6.0 V)
RESONATOR RECOMMENDED CIRCUIT PARAMETER Oscillator frequency (fXT) *2 VDD = 4.5 to 6.0 V Oscillation stabilization time *3 10 s TEST CONDITIONS MIN. 32 TYP. 32.768 MAX. 35 UNIT kHz
XT1
Crystal resonator*1
XT2 330 k
1.0
2
s
C3
C4
XT1
External clock
XT2 Leave Open
XT1 input frequency (fXT)
32
100
kHz
XT1 input high and low level widths (tXTH, tXTL)
10
32
s
*
1. Recommended resonators are shown in following page. 2. Oscillator characteristics only. Refer to the description of AC characteristics for instruction execution time. 3. Oscillation stabilization time is a time required for oscillation to become stabilized after VDD application or STOP mode release.
40
PD75206
CAPACITANCE ( Ta = 25 C, VDD = 0 V )
PARAMETER Input capacitance Except display output Output capacitance Display output Input /output capacitance CIO COUT SYMBOL CIN f = 1 MHz Unmeasured pin returned to 0V TEST CONDITIONS MIN. TYP. MAX. 15 15 35 15 UNIT pF pF pF pF
41
PD75206
RECOMMENDED OSCILLATOR CONSTANTS MAIN SYSTEM CLOCK : CERAMIC (Ta = -40 to +85 C)
EXTERNAL CAPACITANCE (pF) C1 Murata Mfg. Co., Ltd. Kyocera Corp. CSA 4.19MG KBR-2.09MS KBR-3.58MS KBR-4.19MS KBR-4.9MS 33 33 30 68 C2 30 68 4.0 6.0 OSCILLATION VOLTAGE RANGE (V) MIN. 4.0 MAX. 6.0
MANUFACTURER
PRODUCT NAME
MAIN SYSTEM CLOCK : CRYSTAL (Ta = -40 to +85 C)
EXTERNAL CAPACITANCE (pF) C1 HC-49/U 15 C2 15 OSCILLATION VOLTAGE RANGE (V) MIN. 2.7 MAX. 6.0
MANUFACTURER
FREQUENCY (MHz)
HOLDER
Kinseki
4.19
Note
Use a 10 to 33-pF capacitor as the external capacitance C1 of the crystal oscillator for fine-tuning the frequency to a specific value.
42
PD75206
DC CHARACTERISTICS (Ta = -40 to 85 C, VDD = 2.7 to 6.0 V)
PARAMETER SYMBOL VIH1 VIH2 Input voltage high VIH3 VIH4 VIL1 Input Voltage low VIL2 VIL3 Output voltage high VOH Except below Ports 0, 1, RESET X1, X2, XT1 VDD = 4.5 to 6.0 V Port 6 0.7 VDD Except below Ports 0, 1, 6, RESET X1, X2, XT1 VDD = 4.5 to 6.0V, IOH = -1 mA All output pins Ports 4, 5 Output voltage low VOL All output pins ILIH1 ILIH2 ILIL1 ILIL2 ILOH ILOL1 ILOL2 Except X1,X2,XT1 VIN = VDD X1, X2, XT1 Except X1,X2,XT1 VIN = 0 V X1, X2, XT1 All output pins VOUT = VDD Except display output VOUT = 0 V Display output S0 to S9 Display output current IOD T0 to T15 VOUT = VLOAD = VDD - 35 V VPRE = VDD - 9 1 V*1 VDD = 4.5 to 6.0 V VPRE = 0 V VOD = VPRE = VDD - 9 1 V*1 VDD - 2 V VPRE = 0 V VDD = 4.5 to 6.0 V -3 -1.5 -15 -7 30 30 VOD - VLOAD = 35 V VDD = 5 V 10 %*3 VDD = 3 V 10 %*4 VDD = 5 V 10 % HALT mode VDD = 3 V 10 % 40 70 3.0 0.55 600 200 40 5 0.5 0.1 -5.5 -3.5 -22 -15 80 200 1000 120 9.0 1.5 1800 600 120 15 20 10 20 -3 -20 3 -3 -10 IOH = -100 A VDD = 4.5 to 6.0V, IOL = 15 mA VDD = 4.5 to 6.0V, IOL = 1.6 mA IOL = 400 A 0 0 0 VDD-1.0 VDD-0.5 0.4 2.0 0.4 0.5 3 TEST CONDITIONS MIN. 0.7 VDD 0.75 VDD VDD-0.4 0.65 VDD TYP. MAX. VDD VDD VDD VDD VDD 0.3 VDD 0.2 VDD 0.4 UNIT V V V V V V V V V V V V V
Input leakage current high Input leakage current low Output leakage current high Output leakage current low
A A A A A A A
mA mA mA mA k k k mA mA
Built-in pull-down resistor (mask option)
RP6 RL IDD1
Port 6 VIN = VDD Display output 4.19 MHz crystal oscillation C1 = C2 = 15pF
IDD2 Supply current*2 IDD3 IDD4 IDD5
A A A A A A
VDD = 3 V 10 % 32 kHz crystal oscillation*5 HALT mode VDD = 3 V 10 % XT1 = 0 V STOP mode VDD = 5 V 10 % VDD = 3 V 10 %
43
PD75206
*
1. The following external circuit is recommended.
PD75206
+5 V VDD RD9, 1EL VPRE 68 k VLOAD -30 V VSS RD9, 1EL :Zener Diode (NEC) Zener Voltage = 8.29 to 9.30 V
2. Current to the on-chip pull-down resistor and power-on reset circuit (mask option) is not included. 3. When the processor clock control register (PCC) is set to 0011 and is operated in the high-speed mode. 4. When the PCC register is set to 0000 and is operated in the low-speed mode. 5. When the system clock control register (SCC) is set to 1001 and is operated with the subsystem clock with main system clock oscillation stopped. POWER-ON RESET CIRCUIT CHARACTERISTICS (MASK OPTION) (Ta = 40 to +85 C)
PARAMETER Power-on reset operating voltage high Power-on reset operating voltage low Power supply voltage rise time Power supply voltage off time Power-on reset circuit*2 current consumption SYMBOL VDDH TEST CONDITIONS MIN. 4.5 TYP. MAX. 6.0 UNIT V
VDDL
0
0.2
V
tr
10
*1
s
toff VDD = 5 V 10 % IDDPR VDD = 2.7 V
1 10 2 100 20
s
A A
*
1. 2 17/fXX (31.3 ms at fXX = 4.19 MHz) 2. Current with on-chip power-on reset circuit or power-on flag.
VDD
VDDH VDDL
toff
tr
Remarks
Start the power supply smoothly.
44
PD75206
AC CHARACTERISTICS (Ta = -40 to +85 C , VDD = 2.7 to 6.0 V)
PARAMETER SYMBOL TEST CONDITIONS Operation with main system clock tCY Operation with subsystem clock VDD = 4.5 to 6.0 V TI0 input frequency fTI 0 TI0 input high and lowlevel widths tTIH, tTIL Input VDD = 4.5 to 6.0 V SCK cycle time tKCY Output Input Output Input SCK high and low-level widths tKH, tKL VDD = 4.5 to 6.0 V Output Input Output SI setup time (to SCK) SI hold time (from SCK) SO output delay time from SCK tSIK tKSI VDD = 4.5 to 6.0 V tKSO 1000 INT0 Interrupt input high and low-level widths tINTH, INT1 tINTL INT2, 4 RESET low-level width tRSL 10 10 2tCY *2 ns tKCY/2-50 1.6 tKCY/2-150 100 400 300 VDD = 4.5 to 6.0 V 0.83 3 0.8 0.95 3.2 3.8 0.4 165 kHz 114 0 122 125 0.6 VDD = 4.5 to 6.0 V MIN. 0.95 3.8 TYP. MAX. 32 32 UNIT
s s s
MHz
CPU clock cycle time (minimum instruction execution time = 1 machine cycle) *1
s s s s s s s
ns
s
ns ns ns ns
s s s s
45
PD75206
*
1. CPU clock () cycle time is determined by the oscillator frequency of the connected resonator, the system clock control register (SCC) and the processor clock control register (PCC). The cycle time tCY characteristics for power supply voltage VDD when the main system clock is in operation is shown below.
Cycle Time tCY [s]
tCY VS VDD (Main System Clock in Operation) 40 32 30 6 5 4 3 Operation Guaranteed Range
2. 2tCY or 128/fXX is set by interrupt mode register (IM0) setting.
2
1
0.5 0 1 2 3 4 5 6
Power Supply Voltage VDD [V]
46
PD75206
AC Timing Measurement Values (Except X1 and XT1 Inputs)
0.75 VDD 0.2 VDD
Test Points
0.75 VDD 0.2 VDD
Clock Timing
1/fX tXL tXH
X1 Input
V DD - 0.4 V 0.4 V
1/fXT tXTL tXTH
XT1 Input
VDD - 0.4 V 0.4 V
TI0 Timing
1/fTI tTIL tTIH
TI0
47
PD75206
Serial Transfer Timing
tKCY tKL tKH
SCK
tSIK
tKSI
SI
Input Data
tKSO
SO
Output Data
Interrupt Input Timing
tINTL
tINTH
INT0,1,2,4
RESET Input Timing
tRSL
RESET
48
PD75206
DATA MEMORY STOP MODE LOW POWER SUPPLY VOLTAGE DATA RETENTION CHARACTERISTICS (Ta = -40 to +85 C)
PARAMETER Data retention power supply voltage Data retention power supply current *1 Release signal set time Oscillation stabilization wait time *2 SYMBOL VDDDR TEST CONDITIONS MIN. 2.0 TYP. MAX. 6.0 UNIT V
IDDDR tSREL tWAIT
VDDDR = 2.0V 0 Release by RESET Release by interrupt request
0.1
10
A s
217/fX *3
ms ms
*
1. Current to the on-chip pull-down resistor and power-on reset circuit (mask option) is not included. 2. Oscillation stabilization wait time is time to stop CPU operation to prevent unstable operation upon oscillation start. 3. According to the setting of the basic interval timer mode register (BTM) (see below).
BTM3 -- -- -- --
BTM2 0 0 1 1
BTM1 0 1 0 1
BTM0 0 1 1 1
Wait Time (Values at fXX = 4.19 MHz in parentheses) 220/fX (approx. 250 ms) 217/fX (approx. 31.3 ms) 215/fX (approx. 7.82 ms) 213/fX (approx. 1.95 ms)
Data Retention Timing (STOP Mode Release by RESET)
Internal Reset Operation HALT Mode Operating Mode
STOP Mode Data Retention Mode VDD VDDDR STOP Instruction Execution RESET tWAIT tSREL
49
PD75206
Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal)
HALT Mode Operating Mode
STOP Mode Data Retention Mode VDD VDDDR STOP Instruction Execution Standby Release Signal (Interrupt Request) tWAIT tSREL
50
PD75206
13. CHARACTERISTIC CURVES
IDD vs VDD
(Ta = 25 C)
5000 High-Speed Mode (0011) Medium-Speed Mode (0010) Low-Speed Mode (0000)
1000
HALT Mode (0100)
500
Supply Current IDD [A]
Subsystem Clock Operating Mode 100
50
Subsystem Clock HALT Mode
STOP Mode (1000) 10 Power-on reset circuit and power-on flag incorporated
5
X1 4.19 MHz 15 pF 15 pF
X2
XT1
XT2 330 k 32.768 kHz
22 pF
33 pF
1 0 1 2 3 4 5 6
Supply Voltage VDD [V]
Remarks
Values of the processor clock control register (PCC) is indicated in parenthesis.
51
PD75206
IOL vs VOL (Ports 0, 2, 3, 6)
20 (Ta = 25 C)
VDD = 5 V VDD = 6 V 15
Output Current Low IOL [mA]
VDD = 4 V
VDD = 3 V 10
VDD = 2.7 V
5
0 0 1 2 3 4 5
Output Voltage Low VOL [V]
IOH vs (VDD to VOH) (Ports 0, 2, 3, 6)
-20 (Ta = 25 C)
VDD = 5 V -15 VDD = 6 V VDD = 4 V
Output Current High IOH [mA]
-10 VDD = 3 V
-5 VDD = 2.7 V
0 0 1 2 3 4 5
VDD- VOH [V]
52
PD75206
IOL vs VOL (Ports 4, 5)
20 (Ta = 25 C)
VDD = 5 V 6V 15 4V VDD = 3 V
Output Current Low IOL [mA]
VDD = 2.7 V 10
5
0 0 1 2 3 Output Voltage Low VOL [V] 4 5
IOH vs (VDD to VOH) (Ports 4, 5)
-20 (Ta = 25 C)
VDD = 6 V -15 VDD = 5 V
Output Current High IOH [mA]
VDD = 4 V -10
VDD = 3 V -5 VDD = 2.7 V
0 0 1 2 3 4 5
VDD- VOH [V]
53
PD75206
IOD vs (VDD to VOD) (T0 to T15)
-40.0 (Ta = 25 C)
VDD - VPRE = 8 V -30.0 VDD - VPRE = 10 V
Display Output Current IOD [mA]
VDD - VPRE = 6 V
-20.0
VDD - VPRE = 4 V
-10.0
0 0 1 2 3 VDD- VOD [V] 4 5
IOD vs (VDD to VOD) (S0 to S9)
-10.0 VDD - VPRE = 10 V (Ta = 25 C) VDD - VPRE = 8 V
Display Output Current IOD [mA]
VDD - VPRE = 6 V
-5.0
VDD - VPRE = 4 V
0 0 1 2 3 4 5
VDD- VOD [V]
54
PD75206
14. PACKAGE INFORMATION
64 PIN PLASTIC SHRINK DIP (750 mil)
64 33
1 A
32
K L
J I
F D
G
H
N
M
C
B
M
R
NOTE 1) Each lead centerline is located within 0.17 mm (0.007 inch) of its true position (T.P.) at maximum material condition. 2) Item "K" to center of leads when formed parallel.
ITEM MILLIMETERS A B C D F G H I J K L M N R 58.68 MAX. 1.78 MAX. 1.778 (T.P.) 0.500.10 0.9 MIN. 3.20.3 0.51 MIN. 4.31 MAX. 5.08 MAX. 19.05 (T.P.) 17.0 0.25 +0.10 -0.05 0.17 0~15
INCHES 2.311 MAX. 0.070 MAX. 0.070 (T.P.) 0.020 +0.004 -0.005 0.035 MIN. 0.1260.012 0.020 MIN. 0.170 MAX. 0.200 MAX. 0.750 (T.P.) 0.669 0.010 +0.004 -0.003 0.007 0~15 P64C-70-750A,C-1
55
PD75206
64 PIN PLASTIC QFP (14x20)
A B
51 52
33 32
detail of lead end
C
D
S
Q R
64 1
20 19
F G
H
I
M
J
K P N L M
NOTE
Each lead centerline is located within 0.20 mm (0.008 inch) of its true position (T.P.) at maximum material condition.
ITEM A B C D F G H I J K L M N P Q R S
MILLIMETERS 23.60.4 20.00.2 14.00.2 17.60.4 1.0 1.0 0.400.10 0.20 1.0 (T.P.) 1.80.2 0.80.2 0.15 +0.10 -0.05
INCHES 0.9290.016 0.795 +0.008 -0.009 0.551+0.009 -0.008 0.6930.016 0.039 0.039 0.016 +0.004 -0.005 0.008 0.039 (T.P) 0.071 +0.008 -0.009 0.031 +0.009 -0.008 0.006 +0.004 -0.003
0.10 0.004 2.7 0.106 0.10.1 0.0040.004 55 55 3.0 MAX. 0.119 MAX. P64GF-100-3B8,3BE,3BR-2
56
PD75206
64-pin ceramic QFP for ES (reference) (unit : mm) 14.2 12.0
1
64
52 51
18.0
19 20 33 32
1.0
0.4
2.25
20
0.15
Note
1. Care is needed since the metal cap is connected to pin 26 and set to the positive power supply level. 2. Care is needed since the lead of the base is formed obliquely. 3. The lead length is not stipulated since the cutting of the lead ends is not progresscontrolled.
Bottom View
57
PD75206
5
15. RECOMMEDED SOLDERING CONDITIONS
This product should be soldered and mounted under the conditions recommended below. For details of recommended soldering conditions for the surface mounting type, refer to the document "Semiconductor Device Mount Technology" (IEI-1207). For soldering methods and conditions other than those recommended below, contact our salesman. Table 15-1 Surface Mounting Type Conditions
PD75206GF-xxx-3BE : 64-pin plastic QFP (body 14 x 20 mm)
Solderring Method Wave soldering Solderring Conditions Solder bath temperature: 260 C or less, Duration: 10 sec. max., Number of times: Once Preheating temperature : 120 C max. (package surface temperature) Package peak temperature: 230 C, Duration: 30 sec. max. (at 210 C or above), Number of times: Once Package peak temperature: 215 C, Duration: 40 sec. max. (at 200 C or above), Number of times: Once Pin part temperature: 300 C or below , Duration: 3 sec. max. (per device side) Recommended Condition Symbol WS60-00-1
Infrared reflow VPS
IR-30-00-1 VP15-00-1 ---
Pin part heating
*
For the storage period after dry-pack decompression storage conditions are max. 25 C, 65 % RH.
Note Use of more than one soldering method should be avoided (except in the case of pin part heating). Table 15-2 Insertion Type Soldering Conditions
PD75206CW-xxx : 64-pin plastic shrink DIP (750 mil)
Solderring Method Wave soldering (lead part only) Pin part heating Solderring Conditions Solder bath temperature: 260 C or below , Duration: 10 sec. max. Pin part temperature: 260 C or below , Duration: 10 sec. max.
Note
Ensure that the application of wave soldering is limited to the lead part and no solder touches the main unit directly.
58
PD75206
APPENDIX A.
DEVELOPMENT TOOLS
5
The following development tools are available for the development of systems using the PD75206.
IE-75000-R *1 IE-75001-R IE-75000-R-EM*2 Hardware EP-75216ACW-R EP-75216AGF-R EV-9200G-64 PG-1500 PA-75P216ACW PA-75P218GF PA-75P218KB Software IE control program PG-1500 controller RX75X relocatable assembler
In-circuit emulator for 75X series
Emulation board for IE-75000-R and IE-75001-R Emulation prove for PD75216ACW Emulation prov for PD75216AGF, 64-pin conversion socket EV-9200G-64 is also supplied.
PROM programmer PROM programmer adapter for PD75P216ACW and 75P218CW, and is connected to PG-1500. PROM programmer adapter for PD75P218GF, and is connected to PG-1500. PROM programmer adapter for PD75P218KB, and is connected to PG-1500. Host machine * PC-9800 series (MS-DOSTM, Ver. 3.30 to Ver. 5.00A*3) * IBM PC series (PC-DOS
TM
, Ver. 3.1)
*1 Maintenance products 2 Not provided in IE-75001-R 3 Ver. 5.00/5.00A is provided with task swap function, but this function cannot be used with this software.
59
PD75206
5
APPENDIX B.
RELATED DOCUMENTS
Documents related on devices
DOCUMENT User's manual Instruction list Application note 75X series selection guide DOCUMENT NO. IEM-988 IEM-968 IEM-989 IF-151
Documents related on development tools
DOCUMENT IE-75000-R User's manual IE-75001-R User's manual Hardware IE-75000-R-EM User's manual EP-75216ACW-R User's manual EP-75216AGF-R User's manual PG-15000 User's manual RA75X assembler package User's manual Software Instruction PC-9800 series (MS-DOS) base IBM PC series (PC DOS) base Language PG-1500 controller user's manual EEU-730 EEU-704 DOCUMENT NO. EEU-669 EEU-846 EEU-673 EEU-667 EEU-668 EEU-651 EEU-731
Other documents
DOCUMENT Package manual Semiconductor device - Mounting manual NEC semiconductor device quality grade NEC semiconductor device reliability quality control Static electricity discharge (ESD) test Semiconductor device quality guarantee guide Product guide related on microcomputer - Other manufacturers DOCUMENT NO. IEI-635 IEI-616 IEI-620 IEM-5068 MEM-539 MEI-603 MEI-604
Note Be sure to use the latest document for designing.
60
PD75206
GENERAL NOTES ON CMOS DEVICES
1 STATIC ELECTRICITY (ALL MOS DEVICES)
Exercise care so that MOS devices are not adversely influenced by static electricity while being handled. The insulation of the gates of the MOS device may be destroyed by a strong static charge. Therefore, when transporting or storing the MOS device, use a conductive tray, magazine case, or conductive buffer materials, or the metal case NEC uses for packaging and shipment, and use grounding when assembling the MOS device system. Do not leave the MOS device on a plastic plate and do not touch the pins of the device. Handle boards on which MOS devices are mounted similarly .
2
PROCESSING OF UNUSED PINS (CMOS DEVICES ONLY)
Fix the input level of CMOS devices. Unlike bipolar or NMOS devices, if a CMOS device is operated with nothing connected to its
input pin, intermediate level input may be generated due to noise, and an inrush current may flow through the device, causing the device to malfunction. Therefore, fix the input level of the device by using a pull-down or pull-up resistor. If there is a possibility that an unused pin serves as an output pin (whose timing is not specified), each pin should be connected to VDD or GND through a resistor. Refer to "Processing of Unused Pins" in the documents of each devices.
3
STATUS BEFORE INITIALIZATION (ALL MOS DEVICES)
The initial status of MOS devices is undefined upon power application. Since the characteristics of an MOS device are determined by the quantity of injection at the
molecular level, the initial status of the device is not controlled during the production process. The output status of pins, I/O setting, and register contents upon power application are not guaranteed. However, the items defined for reset operation and mode setting are subject to guarantee after the respective operations have been executed. When using a device with a reset function, be sure to reset the device after power application.
61
PD75206
[MEMO]
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. The devices listed in this document are not suitable for use in aerospace equipment, submarine cables, nuclear reactor control systems and life support systems. If customers intend to use NEC devices for above applications or they intend to use "Standard" quality grade NEC devices for applications not intended by NEC, please contact our sales people in advance. Application examples recommended by NEC Corporation Standard : Computer, Office equipment, Communication equipment, Test and Measurement equipment, Machine tools, Industrial robots, Audio and Visual equipment, Other consumer products, etc. Special : Automotive and Transportation equipment, Traffic control systems, Antidisaster systems, Anticrime systems, etc.
M4 92.6
EEPROMTM is a trademark of NEC Corporation. FIP (R) is a trademark of NEC Corporation. MS-DOSTM is a trademark of Microsoft Corporation. PC DOSTM is a trademark of IBM Corporation.

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